As the demand for functions and applications of electronic products increases rapidly, packaging technology has continued to advance toward super high density, miniature, and from single chip to multi-chip, 2D to 3D scale. Consequently, there are advanced packaging structures (i.e. super high density packaging forms) at present, such as wafer level package, 3D package, multi-chip package, and System In Package (SIP), which are distinctly different from conventional packaging in the design, manufacture, and material use. The most ideal situation is to accommodate all circuits in a single silicon chip which is System-on-Chip (SoC). However, besides technical difficulties, integrating ever-complicated circuit functions into a single chip will enlarge the chip size, complicate the chip-making process, and causes reduced yield and increased cost. Therefore, compared with SoC technology, SIP which emphasizes small size, high frequency, high speed, short production cycle, and low cost is the preferred method to realize the above goals and integrate chips with various circuit functions. Based on the requirements of different applications, packaging can be categorized into planar Multi-Chip Module (MCM), Multi-Chip Package (MCP), and 3D stacked packaging structure having multichips which reduce packaging areas more effectively and further use thin chips to cut both the thickness and weight of the stacked package. Hence, the requirement of lightness, thinness, and shortness for advanced packaging structures can be accomplished.
A fan-out wafer-level packaging structure and process thereof are disclosed in Taiwan Patent No. 5,431,255, as shown in FIG. 1, wherein a molding material 14 is on the both sides and the bottom of a chip 12, a dielectric layer pattern 8 that is used to define the structure of a conductive layer 6 is distributed over the chip 12 and the packaging materials 14, and a protective masking layer 4 is coated on the surface of the package. A first conductive bump 10 can reach a second conductive bump 18 through the conductive layer in the above structure to achieve I/O fan out. Further, a manufacturing method for the above packaging structure is also disclosed in the patent. The method comprises: 1) a masking layer (carrier) is coated on a substrate; 2) the masking layer is patterned to expose a portion of the substrate, and a conductive pattern is formed on a part of the masking layer pattern and the exposed substrate; 3) a dielectric layer pattern is formed on the masking layer and on the conductive layer pattern, and a portion of the above conductive layer pattern is exposed; 4) the chip is connected to the above exposed conductive layer pattern using the first conductive bump to form signal connection; 5) the packaging materials is formed on the above chip, and the above substrate is removed after; and 6) the second conductive bump is formed and located on the above exposed conductive pattern, and the packaging units are cut and separated. The patent provides a wafer-level packaging structure having I/O fan-out characteristic; however, the packaging structure does not have stacking characteristic and is unable to meet the requirement of SIP technology.
An electronic packaging structure using a patterned metal layer to achieve I/O fan-out characteristic is disclosed in U.S. Pat. No. 6,288,905, referring to FIG. 2. This packaging structure comprises: a patterned metal layer 110, a thermoplastic or thermosetting dielectric layer 120, via holes 130 and conductive materials 132 filled inside the holes 130, bottom packaging materials 146, and an electronic element 140. Signal transmission of the electronic element of the patent can reach the surface patterned metal layer of the packaging structure through the above conductive via holes; the patterned metal layer also provides a support for the packaging structure in the manufacturing process. However, this packaging structure does not have the stacking characteristic, either; moreover, there are dielectric materials besides via holes between the electronic element and the metal layer, and thus it is not easy to release heat energy generated by the electronic element to the outside of the package along this path.
Accordingly, as system-on-chip (SoC) package is becoming a trend to manufacture multiple chips, such as microelectronics, high frequency communication or actuating sensors, and to reduce the technology cost of stacked packaging and to achieve packaging volume miniaturization, it is a pressing issue to develop a high-density, highly reliable structure and electrical properties, and to design and assemble a packaging structure with multi-microelectronic elements which can make flexible adjustment depending on required application functions.